Integrated buffer circuits for coupling low-output impedance driver to high-input impedance load

ABSTRACT

The combination in a common substrate, of a lateral bipolar transistor operated in the common base mode and a field-effect transistor whose source (or drain) electrode is the collector electrode of said bipolar transistor. A signal applied to the emitter of the bipolar transistor causes a current to flow through the conduction channel of the field-effect transistor. The voltage thereby developed at the electrode common to both transistors, even in response to a small signal current, is of sufficient amplitude to drive a high-input impedance load such as other field-effect transistors embedded in the same substrate.

United States Patent Lee [ 51 Feb. 1, 1972 [$4] INTEGRATED BUFFERCIRCUITS FOR COUPLING LOW-OUTPUT IMPEDANCE DRIVER T0 HIGH-INPUTIMPEDANCE LOAD [72] Inventor: llarry Charles Lee, West Lafayette, lnd.

[73] Assignee: RCA Corporation [22] Filed: Sept. 15, 1969 [21 Appl. No.:858,073

[52] [1.8. CI. ..307/303, 307/304, 317/235 G, g 317/235 Y, 317/235 Z[51] Int. Cl. IIOI| 19/00 [58] Field of Search ..317/235 G, 235 Y, 235Z; 307/303, 304, 205, 221 C, 251, 279

[56] References Cited UNITED STATES PATENTS 3,243,669 3/1966 Sah..3l7/234 3,427,445 2/1969 Dailey ..-...307/205X Lin ..3l7/235 3,283,17011/1966 Buie ..317/23S 3,390,273 6/ 1968 Weckler .317/235 3,450,961 6/l969 Tsaii .317/235 3,461,361 8/ 1969 Delivorias ..3 1 7/ 235 PrimaryExaminer-John W. Hucltert 7 Assistant Examiner-William D. LarkinsAttorney-H. Christoffersen [57] ABSTRACT The combination in a commonsubstrate, of a lateral bipolar transistor operated in the'common basemode and a field-effect transistor whose source (or drain) electrode isthe collector electrode of said bipolar transistor. A signal applied tothe emitter of the bipolar transistor causes a current to flow throughthe conduction channel of the field-effect transistor. The voltagethereby developed at the electrode common to both transistors, even inresponse to a small signal current, is of sufiicient amplitude to drivea high-input impedance load such as other field-effect transistorsembedded in the same substrate.

8 Claims, 5 Drawing Figures ,ToP-MOS. 43' ClRCUIT PATENTED FEB 1 I9723.639.787

sum 1 ur 2 To P-MOS.C|RCUIT.

III l M 2 3| P l6 20 g 26 N-SUBSTRATE I4 Fig. 1B.

lNVljN'l'f/R Harry 6. Lee

ATTORNEY INTEGRATED BUFFER CIRCUITS FOR COUPLING LOW- OUTPUT IMPEDANCEDRIVER TO HIGH-INPUT IMPEDANCE LOAD.

BACKGROUND OF THE INVENTION A characteristic of field-effect transistor(FET) circuits is their extremely high input impedance. Accordingly, theinput signal to such a circuit, while itmay be at a low-current level,must be at a relatively high voltage. n the other hand, bipolar circuitshave low-input impedance and high-current, low-voltage output levels.Problems therefore arise when it is. desired to have a bipolarcircuit,or any circuit with comparable output impedance characteristics, drive aPET circuit.

One solution to the problem above is to employ a PET buffer circuit.However, such a circuit generally requires a multiplicity of components.This is undesirable especially in the integrated circuit technologybecause it, means more expense in making the masks, lower yields andmost importantly, chip area which more advantageously could be used forother circuits. Means also must be provided when employing a buffercircuit forpreventing the buildup of excessive potential across the highimpedance, low capacitance input circuit of the buffer. In addition to.all of this, the buffer circuit introducesundesired time delay.

An object of the present invention is toprovide a buffer circuit of thetype discussed above but which is relatively simple and inexpensive,which requires little chip area, and which results in little time delay.

Another object of the present invention is to provide a buffer circuitwhich, in addition to its usual function, readily may be adapted toperformlogic functions.

Another object of the invention is to provide an improved integratedcircuit which includes, in a very small amount of chip area, transistorsof different operating characteristics.

SUMMARY OF THE INVENTION An integrated semiconductor circuit of specialusefulness as a buffer. The circuit comprises a common substrate with atleast two transistors formed therein. The first is a bipolar transistorwhich includes first and second electrodes of different conductivitythan the region in which they are embedded. The second transistor is ofthe field-effect type and comprises said second electrode anda similarthird electrode spaced from the second electrode and also embedded inthe substrate, the substrate region between these two electrodes servingas a conduction channel. The conductivity of this channel is controlledby another electrode which is insulated from and electrically coupled tosaid channel.

BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings likereference characters denote like components; and:

FIG. 1A is a schematic diagram of an embodiment of the invention;

FIG. 1B is a cross-sectional view of a monolithic integrated circuitembodying the invention;

FIG. 2A is a schematic diagram of another embodiment of the inventionshowing how it may be used as a logic gate;

FIG. 2B is a cross-sectional view of part of the integrated circuit ofFIG. 2A; and

FIG. 3 is a partial cross-sectional view of FIG. 2A taken along line3-3.

DETAILED DESCRIPTION OF THE INVENTION The circuit of FIG. IA shows a PM?bipolar transistor 12 havingfa base 14 connected to ground, an emitter16 coupled to input point 17 and a collector 20. The input point 17 isconnected via resistor 19 to a signal sourcel8. The source I8 may be anycurrent source having a relatively low-voltage output and providing apositive signal, as shown. The resistor 19 shown in phantom view may,not actually be present but represents the sum, of the source impedanceof the signal source and the base-toemitter resistance of transistor 12.It is included in the circuit for purposes of the analysis given later.

The collector 20 of transistor I2 is coupled to a load 22. Load 22includes a P-conductivity type metal-oxide semiconductor (P-MOS) device24 having its source region common with the collector 20 of transistorI2, a drain 26 connected to a source of V,,,, potential and a gateelectrode 30. The gate 30 is connected either to a source of directcurrent (DC) potential of amplitude V or, as a means of minimizingpower; dissipation, tov a clock signal whose maximum amplitude would beV The substrate of transistor 24 is identicaland common to the base oftransistor I2 as shown in FIG. 1B and is connected to ground potential.P-MOS device 24 is a transistor whichis operated as a resistor whoseimpedance is a function of the forward bias applied between the gate andsource of the transistor. Through the value of the resistance is alsodependent on the drain-to-source voltage, it may be assumed that thevalue of the resistance is primarily determined by the gate-to-sourcepotential. Thus, the more negative V or the clock potential, the loweris the drain-to-source impedance of transistor 24.

FIG. 1B is a cross section of the circuit of FIG. IA as it ismanufactured in monolithic integrated circuit form. The identifyingnumbers in FIG. lBare labeled to correspond to their functionaldescription, shown in FIG. 1A. The N-type substrate I4 forms orfunctions as the chassis in which all the components are embedded by thediffusion therein of P-type regions.

Field-efiect transistor 24 is formed by spaced-apart P-regions 20 and 26which define the ends of a conduction channel. The space between the twoP-regions (20 and 26)-the channel-4s overlayed by an insulator layer 31,such as silicon dioxide (SiO,), over which a metal electrode 30, whichdefines the gate electrode of the transistor, is placed.

In a P-MOS transistor, the source is defined as that electrode of thetwo conduction channel electrodes having the most positive potentialapplied thereto. Therefore in FIGS. IA and IB P-region 20 which willnormally be at a positive potential with respect to P-region 26 iscalled the source. But it is to be kept in mind that an PET is abidirectional device and therefore may conduct current in eitherdirection. It is therefore clear that an electrode (20 or 26) definingan end of the conduction channel may be the source for one direction ofconduction and the drain for the opposite direction of conduction.

FIG. 1B shows that PNP lateral bipolar transistor 12 is formed byspacing P-region 16 (the emitter of transistor 12) from the adjacentP-region 20 (the collector of transistor 12), by anarrow region of the Nconductivity type substrate 14, the latter acting as the base oftransistor 12. The F ET transistor 24 manufactured on the same substrateconsists of just two diffused regions, one of the two regions being aregion (electrode 20) common to both transistors.

In the operation of the circuit, a signal source 18 generates pulseshaving a maximum amplitude of +V volts and a minimum value of groundpotential, as shown in FIG. IA. These pulses cause emittercurrent (1,)to flow into the emitter-base region of transistor 12. The current I,equals ap proximately the amplitude of the signal (-l-V) minus theemitter-to bjase drop of transistor 12 (V,.,,) divided by the resistanceI9 which includes the source impedance of signal source 18 and the inputresistance of transistor 12. [I,=(+V V,,,)/R,,]. The values of +V, V,and R could typically be, respectively, 5.4 volts, 0.6 voltsand 2,000ohms giving an I of 2.4 milliamps. The emitter current 1, causes acollector current I to flow which is related to I, by the common baseforward current transfer ratio (a). That is, I is equal to 0d,.

Transistor I2 is known as a lateral transistor and its a is generallylow. However, even if a is 0.5 (which is an extremely and improbably lownumber) the output voltage (V,) at the collector 20 will be driven closeto 0 volts-whenever transistor I2 is madeto conduct. V, is equal to--V,,,, plus all multiplied by the drain-to-source resistance os) oftransistor 24 [V,

x-V,,,,+al,, R,,,-]. Assuming, by way of example, that R is 10 K. ohmsand that -V,,,, equals 1 2 volts, a maximum al,=l,. of 1.2 milliampswill be sufficient to drive V between volts and V,,,, volts. However,since the input impedance of P- MOS circuits (not shown) which areconnected to the collector 20 of transistor 12 is of the order of l0ohms, there is no reason why R cannot be made much larger than K. ohms.Thus, for example if R is made equal to l megohm (10 ohms), an 1 of0.012 milliamps would be sufficient to drive the collector of transistor12 between V,,,, and 0 volts.

The current generated by the signal source thus flows into the emitterof transistor 12 and causes a collector current to flow. The collectorcurrent flows into an extremely high impedance thereby providing highvoltage gain.

The low-output voltage of the signal source which may be either acurrent generator or a voltage source having a highsource impedance isthus converted into a large voltage swing. Thus, standard bipolar logiccircuits such as diode-transistor logic (DTL) or transistor-transistorlogic (TTL) can be directly coupled to the interface circuit of theinvention. Also, linear circuits operated at relatively low supplylevels and with low-voltage outputs can now be directly coupled to theFET chip.

A further advantage of the proposed circuit is that it presents anextremely low-input impedance to the external world while beingcompatible with very high impedances at its output. Thus, whileproviding the benefits of impedance transformation, the circuit of theinvention provides protection for the FET circuit by presenting thebuildup of excessive voltages across the input terminals. Since thevoltage across the input can never go very high, this circuit eliminatesthe need for protective circuits which have to be connected across theinputs of FET circuits.

In the circuit of FIG. 2A the level converter is connected as a logicgate whose input is compatible with various bipolar logic circuits andwhose output is compatible with the voltage levels present on the array.Transistor 12 is now shown having a multiplicity of emitters which forease of illustration is limited to three emitters 16a, 16b and 16c. Eachemitter is coupled to a different source of signal denoted respectivelye e and e,. The load 22 network shown in FIG. 2A contains a transistor24 which is identical to that shown in FIG. 1A, but now transistor 24has its gate and drain connected together and coupled to a clock signal(#1.

Load 22 also includes a capacitor 40 having one end connected in commonwith collector-source region and the other end connected to a terminal41 to which a clock signal denoted by 1112 is applied.

The output signal generated at the collector-source region 20 is coupledto the rest of the integrated circuit by gating transistor 42 whose gateis also coupled to 2.

The circuit of FIG. 2A (with transistor 42 omitted) is shown inintegrated form in FIG. 2B. Bipolar transistor 12, as in FIG. I, has anemitter region 16, a collector region 20 and a base region which is partof substrate 14. FET transistor 24 also uses regions 20 as one of itssource and drain electrodes and region 26 as the other one of its sourceand drain electrodes. The capacitor 40 is formed by depositing a thininsulator layer over part of collector-source region 20 and depositing ametallic electrode 41 over this region. Capacitor 40 is thus formedhaving one end common to the collector of bipolar device 12 and theother to a metallic electrode to which a signal may be applied.

FIG. 3 shows in cross-sectional view, taken along the line 3-3 of FIG.2B, the structure of the multiple emitters.

The l clock signal functions to precharge the collectorsource region 20.The clocks, 11:1 and 52 vary from 0 volts to, let us assume, a negativepotential of -V volts which is larger than V,,,, volts. When dal goes toV the potential at collector-source 20 goes to approximately --V volts,if and only if the input voltage applied to emitters 16a, 16b and 16c isequal to or less than 0 volts. Note that the threshold voltage (V oftransistor 24 prevents the potential at collector-source 20 from goingmore negative than V -V l when only d is applied. If, a positive voltageis applied to any one of the emitter leads, the collector source 20 isclamped to ground potential. Thus, when l makes an excursion from 0 toV, volts if all the inputs are grounded then the capacitance associatedwith collector-source 20 is precharged to approximately V volts. If, onthe other hand, one or all of the input signals are positive, thecapacitance associated with the collector-source region 20 will bedischarged and the potential at 20 substantially equal to 0 volts.

Gating transistor 42 is enabled during 4:2 time (i.e., only so long as412 is at V, volts.) The purpose of da' and capacitor 40 is to enhancethe signal level and to provide a time slot for readout which occurswhen @112 goes to V volts. Thus, when 482 goes from 0 to V, volts itopens transmission gate 42 and transmits the signal at collector 20 toother circuits on the P- MOS array.

The role of d 2 and capacitor 40 is best appreciated by examining thecircuit operation. If the potential at collectorsource 20 is 0 volts, is(AC) coupled by means of capacitor 40 to P-region 20. If either e,, e,or e: is high (+V) transistor 12 is conducting and collector-source 20is at approximately 0 volts. #22 when first applied causes a sharpnegative spike which is quickly discharged to ground potential.

If, on the other hand, 2,, e; and e, are low (0 volts) thecollector-source region is already charged to a negative potential bydzl the application of 2 causes more negative charge to flows across thereverse PN junction (P-region 20 and N substrate l4) capacitance. Thepotential at collector-source 20 is thus made even more negative thanV,. When transmission gate 42 is enabled a larger voltage than V, iscoupled to the next stage thereby obviating any problem that might arisedue to the threshold voltage offset of transistor 24 which limits thepotential at collector-source 20 to a threshold voltage drop above V,.The use of capacitor 40 and 422 thus ensures the generation ofwell-defined, large amplitude signals for transmission to the system.The operation of the circuit as a logic gate is best understood by firstdefining the voltage levels in logic equivalent. Thus, for the positivelogic levels (the inputs to transistor 12) ground potential is logic 0"and a positive voltage +V is logic fl; and for the negative logic levels(the output of transistor 12 and remainder of chip) ground potential islogic 0" and a negative voltage (V,) is logic l Based on the previousdiscussion the output (V at collector-source 20 is V, (or more)volts-logic l"when the input signals e =e =e =0 volts-logic 0."

The output V, may thus be expressed as V W. This is the classicalexpression of a NOR output and transistor 12 with its multiple emittersthus functions as a NOR gate.

It should be noted that using the logic definitions above stated andusing but one emitter electrode as in FIG. [A that the circuit of theinvention operates as an (logic) inverter.

The fabrication of the lateral transistor shown in FIGS. 1A, 1B and asshown in FIG. 2 with multiple emitters does not require any extra stepsin the present P-MOS process.

Capacitor 40 shown in FIG. 2 is also easily fabricated by depositing aninsulating layer over a part of region 20 and by putting a metalelectrode (41) over the insulator. The addition of 51 and 2 which serveto precharge the collector region and to read out the information at thecollector at a given time enable the impedance of transistor 24 to bemade in what is called the ratioless form. That is, since (#1 prechargescollector-source 20 and 2 enhances the potential at the collector theratio of the impedance of transistor 24 may be optimized for a systemconsideration such as speed of operation and is not limited to animpedance ratio which is required for the conduction or nonconduction ofthe next stage. The ratioless feature of the load in combination withthe lateral PNP inverter function enables extremely fast operation. Withthis type of converter, it is feasible to decode DTL or 'I'TL outputs atrates determined by the DTL and 'I'TL logic circuits. The circuit of theinvention with multiple emitter electrodes is thus ideally suited formemory decoding, multiplex decoding or other high speed positive voltagelogic to P-MOS array level converters.

Though the circuits have been shown using a substrate of N- conductivitytype with diffused P-regions it should be obvious that the conductivitytypes could be reversed. Also, though the devices shown areinsulated-gate field-effect devices it should be clear that theinvention is also applicable to any of the known types of field-effectdevices.

What is claimed is:

l. An integrated semiconductor circuit comprising, in combination:

a substrate of first conductivity type;

a bipolar transistor comprising first and second regions of secondconductivity type spaced apart along a surface of said substrate andextending into said substrate for forming the collector and emitterregions of said bipolar transistor; field-effect transistor comprising athird region of said second conductivity type extending into saidsubstrate spaced apart from said second region, said second and thirdregions forming source and drain electrodes of, and the region of thesubstrate between them forming the conduction channel of, saidfield-effect transistor, an insulating layer lying on the surface ofsaid conduction channel, and a metallic electrode on said insulatinglayer for controlling the conductivity of said channel; output meanscoupled to said second region;

means for applying a first potential to said first region; and

means for applying a second potential to said metallic electrode in adirection to forward bias said field-effect transistor.

2. The combination as claimed in claim 1 further including means forapplying ground potential to said substrate.

3. The combination as claimed in claim 1 wherein one of said first andsecond conductivity type is P-type semiconductor material and the otherone of said first and second conductivity type is N-type semiconductormaterial.

4. The combination comprising:

a substrate of first conductivity type; first, second and third distinctregions of second conductivity type spaced apart along a surface of saidsubstrate and extending into said substrate;

a lateral bipolar transistor operated in the common base mode whose baseis common to said substrate, said transistor having at least one emitterelectrode for the application thereto of input signals and a collectorregion, said emitter comprising said first region and said collectorregion comprising said second region;

a field-effect transistor output means coupled to said second regionhaving source and drain regions defining the ends of a conduction pathand a control electrode, wherein one of said source and drain regions issaid collector region and the other one of said source and drain regionsis said third region; and means for applying a potential to said controlelectrode in a direction to forward bias said field effect transistor 5.The combination comprising:

a substrate of given conductivity type;

a first lateral bipolar transistor operated in the common base modewhose base is common to said substrate, said transistor having aplurality of emitter electrodes for the application thereto of inputsignals and a collector region; I

a field-effect transistor embedded in said substrate having source anddrain regions defining the ends of a conduction path and a controlelectrode, wherein one of said source and drain regions is saidcollector region; and

output means coupled to said collector region.

6. The combination as claimed in claim 5, further including a pluralityof input signals, each signal being applied to a different one of saidemitter electrodes, and wherein in response to the presence of saidsignals a current is generated in said bipolar transistor which flowsthrough said source-drain conduction path.

7. The comblnatlon as claimed in claim 5, further Including a capacitorhaving two electrodes, one electrode being common to said collectorregion.

8. The combination as claimed in claim 7, further including first andsecond sources of clock signals, wherein said first source is coupled tothe gate electrode of said field-effect transistor and wherein saidsecond source is coupled to the other electrode of said capacitor.

Patent No. 3:639:787 Dated Fe ruary 1, 1972 Inventor(s) Harry CharlesLee It is certified that error appears in the above-identified patentand that said Letters Patent are hereby corrected as shown below:

Column 2 Q line 16 change "Through" to ---T hough---.

Column 3 line 1 change "X" to line 57 change "regions" to ---region-.

Column 4 line 20 after "volts", insert ---the clock signal 2 which goesfrom O to -V vo1ts,

Column 6 after line 7 insert ---output means coupled to said secondregion---.

line 8 delete "output means coupled to said 1 second Qigned and sealedthis 29th day 05 August 1972.

(SEAL) Attest;

,v EDWARD M.FLETCHER.ZJ1R, ROBERT GOTTSCHALK Attesting OfficerCommissioner of Patents FORM po'mso HO'GB) USCOMM-DC 60376-F'69 fl U S.GOVERNMEN! PRINYING OFFICE 1969 0-356-3J4 Disclaimer 3,639,787.-HawyCharles Lee, West Lafayette, Ind. INTEGRATED BUF- FER CIRCUITS FORCOUPLING LOW OUTPUT IMPED- ANCE DRIVE TO HIGH INPUT IMPEDANCE LOAD.Patent dated. Feb. 1, 1972. Disclaimer filed June 8, 1972, by theassignee, RCA Corporation. Hereby enters this disclaimer to claims 1through 4 of said patent.

[Ofiicial Gazette N o vember 6, 1.973.]

1. An integrated semiconductor circuit comprising, in combination: asubstrate of first cOnductivity type; a bipolar transistor comprisingfirst and second regions of second conductivity type spaced apart alonga surface of said substrate and extending into said substrate forforming the collector and emitter regions of said bipolar transistor; afield-effect transistor comprising a third region of said secondconductivity type extending into said substrate spaced apart from saidsecond region, said second and third regions forming source and drainelectrodes of, and the region of the substrate between them forming theconduction channel of, said field-effect transistor, an insulating layerlying on the surface of said conduction channel, and a metallicelectrode on said insulating layer for controlling the conductivity ofsaid channel; output means coupled to said second region; means forapplying a first potential to said first region; and means for applyinga second potential to said metallic electrode in a direction to forwardbias said field-effect transistor.
 2. The combination as claimed inclaim 1 further including means for applying ground potential to saidsubstrate.
 3. The combination as claimed in claim 1 wherein one of saidfirst and second conductivity type is P-type semiconductor material andthe other one of said first and second conductivity type is N-typesemiconductor material.
 4. The combination comprising: a substrate offirst conductivity type; first, second and third distinct regions ofsecond conductivity type spaced apart along a surface of said substrateand extending into said substrate; a lateral bipolar transistor operatedin the common base mode whose base is common to said substrate, saidtransistor having at least one emitter electrode for the applicationthereto of input signals and a collector region, said emitter comprisingsaid first region and said collector region comprising said secondregion; a field-effect transistor output means coupled to said secondregion having source and drain regions defining the ends of a conductionpath and a control electrode, wherein one of said source and drainregions is said collector region and the other one of said source anddrain regions is said third region; and means for applying a potentialto said control electrode in a direction to forward bias said fieldeffect transistor
 5. The combination comprising: a substrate of givenconductivity type; a first lateral bipolar transistor operated in thecommon base mode whose base is common to said substrate, said transistorhaving a plurality of emitter electrodes for the application thereto ofinput signals and a collector region; a field-effect transistor embeddedin said substrate having source and drain regions defining the ends of aconduction path and a control electrode, wherein one of said source anddrain regions is said collector region; and output means coupled to saidcollector region.
 6. The combination as claimed in claim 5, furtherincluding a plurality of input signals, each signal being applied to adifferent one of said emitter electrodes, and wherein in response to thepresence of said signals a current is generated in said bipolartransistor which flows through said source-drain conduction path.
 7. Thecombination as claimed in claim 5, further including a capacitor havingtwo electrodes, one electrode being common to said collector region. 8.The combination as claimed in claim 7, further including first andsecond sources of clock signals, wherein said first source is coupled tothe gate electrode of said field-effect transistor and wherein saidsecond source is coupled to the other electrode of said capacitor.